1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a MOS transistor capable of reducing P-N junction leakage current generated by substrate defects.
2. Background of the Invention
As the integration level of semiconductor memory devices increases, the integration level is progressing to a DRAM (dynamic random access memory) device having a size of a gigabit or more. Since components of a gigabit unit device are scaled down to less than 0.18 xcexcm, the likelihood that stress may occur increases greatly.
If the stress surpasses a critical value, dislocation may be generated in the device""s silicon substrate to relieve the stress. Due to the scaling down, the process of forming a device isolation area converts a LOCOS (local oxidation of silicon) into an STI (shallow trench isolation). However, the STI may apply more stress to the semiconductor substrate than the LOCOS. As mentioned in an article entitled xe2x80x9cStress-induced Dislocation in Silicon Integrated Circuitsxe2x80x9d (P. M. Fahey et al., IBM J. RES. DEVELOP, v. 36, p. 158, 1992), it is increasingly reported to improve junction damage generated by dislocation and extended defect.
In the fabricating process of a semiconductor, the ion implanting technique is important in the method for fabricating a P-N junction of a device due to the easy implementation of a doping concentration and a doping profile. However, ions having high energy can penetrate a single crystalline silicon during this ion implanting process. If the doping concentration surpasses a critical value, then the crystallinity of the silicon substrate is broken to form an amorphous layer. The crystallinity of the amorphous layer is restored through a subsequent annealing step. During the annealing, remaining defects are collected to generate an extended defect, a stacking fault, and a dislocation loop (as discussed, for example, in xe2x80x9cFormation of Extended Deffects in Silicon by High Energy Implantation of B and Pxe2x80x9d, J. Y. Cheng et. al., Phys. v. 80 (4) p. 2105, 1996; xe2x80x9cAnnealing Behaviours of Dislocation Loops Near the Projected Range in High-dose As-Implanted (001) Sixe2x80x9d, S. N. Hsu et. al., J Appi. Phys. v. 86 (9). p. 4503, 1990).
FIG. 1A is an XTEM (X-transmission electron microscopy) photograph illustrating a defect in a prior semiconductor substrate. Referring to FIG. 1A, if the dislocation, extended defect, and stacking fault penetrate a P-N junction area xe2x80x98Axe2x80x99 of a semiconductor device, then abnormal junction characteristics are generated.
FIG. 1B is an SEM (scanning electron microscopy) photograph illustrating a defect in a prior semiconductor substrate. Referring to FIG. 1B, defects are generated in an edge portion xe2x80x98Bxe2x80x99 adjacent to a device isolation area and an active area due to the ion implanting process. If a reverse bias voltage is applied to the P-N junction, the reverse bias current to the P-N junction is abnormally applied due to the defects.
FIG. 2 is a graph illustrating electrical characteristics of a P-N junction in a prior semiconductor device. Referring to FIG. 2, in the case that a reverse bias voltage is applied to the P-N junction of the prior semiconductor device, a xe2x80x98Cxe2x80x99 curve depicts reverse bias current at an abnormal junction, and a xe2x80x98Dxe2x80x99 curve depicts reverse bias current at a normal junction. It is shown that the reverse bias current at the abnormal junction is greater than the reverse bias current at the normal junction. These characteristics may increase standby current, which may create a severe problem in fabricating a low power consumption device, result in failing components, and reduce yield.
A method consistent with the present invention provides for a semiconductor device capable of forming a stable P-N junction by isolating lattice defects, such as a dislocation, an extended defect, and a stacking fault, from a P-N junction area.
According to the present invention, a gate electrode is formed on a semiconductor substrate. A conductive impurity is implanted into the semiconductor substrate on both sides of the gate electrode to form a source/drain area. A non-conductive impurity is implanted into the source/drain area to form a precipitate area.
According to another aspect of the present invention, a first conductive impurity is implanted into a semiconductor substrate to form a well area. A gate electrode is formed on the well area. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to form a first precipitate area to a first depth. A second conductive impurity is implanted into the well area on both sides of the gate electrode to form a source/drain area to a second depth which can be relatively shallower than the first depth. A second non-conductive impurity is implanted into the source/drain area to form a second precipitate area.
A transistor consistent with the present invention comprises a first conductive well area formed in a semiconductor substrate, a first precipitate area formed to a first depth by implanting a first non-conductive impurity into the first conductive well, a gate electrode formed on the first conductive well, a second conductive source/drain area formed in the first well area on both sides of the gate electrode to a second depth which can be relatively shallower than the first depth, and a second precipitate area formed by implanting a second non-conductive impurity into the source/drain area.
In the method consistent with the present invention, a first non-conductive impurity is implanted into the well area to form a first precipitate area which can control substrate defects. A second non-conductive impurity is implanted into the source/drain area to form a second precipitate area which can also control substrate defects. As a result, substrate defects such as dislocation, extended defect, and stacking fault are isolated from a P-N junction area, thereby forming a stable P-N junction.